1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, and to a liquid crystal display device including the nonvolatile semiconductor storage device. More particularly, the invention relates to an interconnection arrangement of control gates and selection gates of NAND nonvolatile memory cell units in a nonvolatile semiconductor storage device.
2. Description of the Related Art
The recent advancement of the semiconductor technology, particularly, the development of a micro-processing technique and a three-dimensional processing technique (by which memory cells are stacked perpendicularly to a semiconductor substrate surface for increasing the number of memory cells provided in a semiconductor storage device), makes it possible to achieve the memory cell size reduction and capacity increase of a nonvolatile semiconductor storage device. There are various types of nonvolatile semiconductor storage devices which have different circuit configurations and functions. Among these nonvolatile semiconductor storage devices, flash EEPROMs (hereinafter referred to as “flash memories”) are most widely used, particularly, for large storage capacity applications. The flash memories are roughly classified into a NOR type and a NAND type. The NOR flash memory includes one transistor per cell, while the NAND flash memory includes a plurality of memory cell transistors arranged in series and selection transistors provided at opposite ends of the cell arrangement. In the NAND flash memory, a bit line contact and a source line contact are shared by the plurality of memory cell transistors, so that a memory cell area is reduced. Therefore, the NAND flash memory having a smaller memory cell area is suitable for the large storage capacity applications. The NOR flash memory generally performs a programming operation by utilizing channel hot electrons, and performs an erasing operation by utilizing FN tunneling. In the programming operation, voltages of about 10V, about 0V and about 6V are applied to a control gate, a source and a drain, respectively. In the erasing operation, voltages of about −10V and about 5V are applied to the control gate and a P well, respectively, and the source and the drain are opened. On the other hand, the NAND flash memory performs a programming operation and an erasing operation by utilizing FN tunneling. In the programming operation, a voltage of about 20V is applied to a control gate, and a voltage of about 0V is applied to a source and a drain. In the programming operation, a voltage of about −20V is applied to the control gate, and about 0V is applied to the source and the drain. Since the FN tunneling is utilized for the programming operation in the NAND flash memory, the NAND flash memory requires application of higher voltages than the NOR flash memory (see, for example, Flash Memory Technology Handbook authored by Fujio Masuoka and published by Science Forum, Aug. 1993).
FIG. 9 is a block diagram illustrating memory blocks of the prior art NAND flash memory including memory cell units by way of example. A memory cell selecting operation to be performed by the prior art NAND flash memory will be described with reference to FIG. 9.
As shown in FIG. 9, the flash memory 100 includes four memory blocks 101, 102, 103, 104 each including four memory cell unit groups. The memory cell unit groups each include four memory cell units each including two memory cells. Sixteen selection gate lines SG1a to SG1p (any one of which is designated as “SG1”), sixteen selection gate lines SG2a to SG2p (any one of which is designated as “SG2”), sixteen control gate lines CG1a to CG1p (any one of which is designated as “CG1”) and sixteen control gate lines CG2a to CG2p any one of which is designated as “CG2”) are provided for driving selection gates and control gates of the memory cell units. For uniquely selecting each of the memory cells, SG1 decoders 105aSG1 to 108pSG1 and SG2 decoders 105aSG2 to 108pSG2 are respectively provided for the selection gate lines SG1a to SG1p and the selection gate lines SG2a to SG2p, and CG1 decoders 105aCG1 to 108pCG1 and CG2 decoders 105aCG2 to 108pCG2 are respectively provided for the control gate lines CG1a to CG1p and the control gate lines CG2a to CG2p. Four bit lines BLa to BLd are connected to the selection gate lines SG1a to SG1p, SG2a to SG2p and the control gate lines CG1a to CG1p, CG2a to CG2p in an intersecting manner. The bit lines BLa to BLd extend through all the blocks, and are respectively connected to drains of the memory cell units in each of the memory cell unit groups in each of the memory blocks.
When an address signal A[4:1], i.e., four address signals A4 to A1, is inputted to a predecoder 113 from an external pad, the predecoder 113 selects one of four SG2-decoder selection signals SSGD2a to SSGD2d and one of four CG2-decoder selection signals SCGD2a to SCGD2d on the basis of the address signals A4 and A3, and selects one of four SG1-decoder selection signals SSGD1a to SSGD1d and one of four CG1-decoder selection signals SCGD1a to SCGD1d on the basis of the address signals A2 and A1. More specifically, the predecoder 113 selects the signals SSGD2a, SCGD2a where A4=0 and A3=0. The predecoder 113 selects the signals SSGD2b, SCGD2b where A4=0 and A3=1. The predecoder 113 selects the signals SSGD2c, SCGD2c where A4=1 and A3=0. The predecoder 113 selects the signals SSGD2d, SCGD2d where A4=1 and A3=1. The predecoder 113 selects the signals SSGD1a, SCGD1a where A2=0 and A1=0. The predecoder 113 selects the signals SSGD1b, SCGD1b where A2=0 and A1=1. The predecoder 113 selects the signals SSGD1c, SCGD1c where A2=1 and A1=0. The predecoder 113 selects the signals SSGD1d, SCGD1d where A2=1 and A1=1.
When the signals SSGD2a, SCGD2a are selected, circuits of an SG2 decoder 109SG2 and an SG1 decoder 109SG1 in a decoder group 109 are turned on, and circuits of a CG2 decoder 109CG2 and a CG1 decoder 109CG1 in the decoder group 109 are turned on. Similarly, when the signals SSGD2b, SCGD2b are selected, circuits of an SG2 decoder 110SG2 and an SG1 decoder 110SG1 in a decoder group 110 are turned on, and circuits of a CG2 decoder 110CG2 and a CG1 decoder 110CG1 in the decoder group 110 are turned on. When the signals SSGD2c, SCGD2c are selected, circuits of an SG2 decoder 111SG2 and an SG1 decoder 111SG1 in a decoder group 111 are turned on, and circuits of a CG2 decoder 111CG2 and a CG1 decoder 111CG1 in the decoder group 111 are turned on. When the signals SSGD2d, SCGD2d are selected, circuits of an SG2 decoder 112SG2 and an SG1 decoder 112SG1 in a decoder group 112 are turned on, and circuits of a CG2 decoder 112CG2 and a CG1 decoder 112CG1 in the decoder group 112 are turned on.
When the signals SSGD1a, SCGD1a are selected, an SG2 decoder 105aSG2, an SG1 decoder 105aSG1, a CG2 decoder 105aCG2 and a CG1 decoder 105aCG1 in a decoder group 105 are turned on. When the signals SSGD1b, SCGD1a are selected, an SG2 decoder 105bSG2, an SG1 decoder 105bSG1, a CG2 decoder 105bCG2 and a CG1 decoder 105bCG1 in the decoder group 105 are turned on. When the signals SSGD1c, SCGD1c are selected, an SG2 decoder 105cSG2, an SG1 decoder 105cSG1, a CG2 decoder 105cCG2 and a CG1 decoder 105cCG1 in the decoder group 105 are turned on. When the signals SSGD1d, SCGD1d are selected, an SG2 decoder 105dSG2, an SG1 decoder 105dSG1, a CG2 decoder 105dCG2 and a CG1 decoder 105dCG1 in the decoder group 105 are turned on.
Further, where an address signal A0=0 is inputted, the control gate lines connected to the CG1 decoders are selected. Where an address signal A0=1 is inputted, the control gate lines connected to the CG2 decoders are selected.
Next, an explanation will be given to a memory cell selecting operation to be performed when an address signal A[4:0]=00000 is inputted. The predecoder 113 selects the signals SSGD2a, SCGD2a, SSGD1a and SCGD1a. Thus, the SG2 decoder 109SG2, the SG1 decoder 109SG1, the CG2 decoder 109CG2 and the CG1 decoder 109CG1 in the decoder group 109, and the SG2 decoder 105aSG2, the SG1 decoder 105aSG1, the CG2 decoder 105aCG2 and the CG1 decoder 105aCG1 in the decoder group 105 are turned on. Then, the selection gate lines SG2a, SG1a are selected. Since the address signal A0 is A0=0, the control gate line CG1a connected to the CG1 decoder 105aCG1 is selected. In a writing operation, a writing voltage generating circuit 114 is turned on by a writing enable signal WEN, whereby a writing voltage is applied to the decoders. Thus, voltages for the writing are respectively applied to the selected selection gate lines and control gate lines. In an erasing operation, an erasing voltage generating circuit 115 is turned on by an erasing enable signal EEN, whereby an erasing voltage is applied to the decoders. Thus, voltages for the erasing are respectively applied to the selected selection gate lines and control gate lines. Signals to be selected for respective status values of the address signals A0 to A4 are shown in Tables 1 to 3. Particularly, Table 1 shows selection signals to be applied to the decoder groups 109 to 112, and Table 2 shows selection signals to be applied to the decoder groups 105 to 108. Table 3 shows the selection gate lines SG2, SG1 and the control gate line CG to be selected.
TABLE 1A4A3Selection signals00SSGD2aSCGD2a01SSGD2bSCGD2b10SSGD2cSCGD2c11SSGD2dSCGD2d
TABLE 2A2A1Selection signals00SSGD1aSCGD1a01SSGD1bSCGD1b10SSGD1cSCGD1c11SSGD1dSCGD1d
TABLE 3Selected CGA4A3A2A1Selected SG2Selected SG1A0 = 1A0 = 00000SG2aSG1aCG2aCG1a01SG2bSG1bCG2bCG1b10SG2cSG1cCG2cCG1c11SG2dSG1dCG2dCG1d0100SG2eSG1eCG2eCG1e01SG2fSG1fCG2fCG1f10SG2gSG1gCG2gCG1g11SG2hSG1hCG2hCG1h1000SG2iSG1iCG2iCG1i01SG2jSG1jCG2jCG1j10SG2kSG1kCG2kCG1k11SG2lSG1lCG2lCG1l1100SG2mSG1mCG2mCG1m01SG2nSG1nCG2nCG1n10SG2oSG1oCG2oCG1o11SG2pSG1pCG2pCG1p
However, the NAND flash EEPROM described above has a smaller memory cell area and a smaller area available for routing the word lines than the NOR flash EEPROM. The NAND flash memory utilized a higher writing voltage and a higher erasing voltage than the NOR flash memory, so that the size of each of the transistors should be increased. Therefore, the routing of interconnections between the memory cells and the word line decoders and the layout of the decoders become more difficult with the size reduction and capacity increase of the semiconductor device.